A technique disclosed in the present invention relates to a solid-state image sensor in which a plurality of photoelectric conversion portions are arranged in an array, and a manufacturing method thereof.
With a recent growing demand for a higher pixel count and a smaller size of solid-state image sensors, a higher image quality has also been required for the solid-state image sensors. It is therefore necessary to reduce the pixel size and to suppress noise.
One of the most popular types of conventional solid-state image sensors is CMOS (complementary metal oxide semiconductor) solid-state image sensors, that is, CMOS sensors. In a circuit of a CMOS sensor, a plurality of photoelectric conversion portions are arranged in an array, and each pixel cell accumulates charges optically generated in the substrate. Each pixel cell therefore includes a photodiode, a photogate, or a photoconductor which covers a doped region of the substrate. Moreover, a read circuit is connected to each pixel cell. The read circuit includes a charge transfer portion which is formed on the substrate at a position adjacent to the photodiode, the photogate, or the photoconductor having a sense node. The sense node is typically a floating diffusion node, and is connected to a gate of a source follower output transistor. Moreover, the CMOS sensor includes at least one transfer transistor for transferring charges from a charge accumulating region of the substrate to the floating diffusion node, and may further include a reset transistor for resetting the diffusion node to a predetermined charge level before charge transfer.
In the conventional solid-state image sensor having the above structure performs the following processes by active elements of the pixel cells: (1) conversion from photons to charges; (2) accumulation of image charges; (3) charge transfer to the floating diffusion node; (4) resetting the floating diffusion node to a known state before charge transfer to the floating diffusion node; (5) pixel selection for reading; and (6) output and amplification of a signal representing charges. The charges transferred to the floating diffusion node are converted to a pixel output voltage by the source follower output transistor. Note that, typically, photosensitive elements of the pixels of the solid-state image sensor are either depleted p-n junction photodiodes, or electric-field induced depletion regions under the photogates.
FIG. 14 is a structural diagram of a conventional solid-state image sensor. More specifically, FIG. 14 is a schematic plan view of a CMOS image sensor 100 which has 1-pixel, 4-transistor (4T) type pixel cells having a typical structure.
As shown in FIG. 14, a photodiode region 131 serving as a charge accumulating region is formed in a surface region of a not-shown substrate. The substrate is made of, for example, silicon. A floating diffusion region (sense node) 137 is formed adjacent to the photodiode region 131. A transfer gate 125 of a transfer transistor is formed over the substrate so as to extend over the photodiode region 131 and the floating diffusion region 137. The transfer gate 125 transfers photoelectric charges generated in the photodiode region 131 to the floating diffusion region 137.
A gate 134 of a reset transistor, a gate 135 of a source follower transistor, and a gate 136 of a row select access transistor are further formed over the not-shown substrate. The floating diffusion region 137 is connected to the gate 135 of the source follower transistor. The source follower transistor supplies an output signal to the row select access transistor. The gate 136 of the row select access transistor selectively gates an output signal to a contact 132 which is formed in a source/drain region 133 doped with impurities having n-type conductivity. The reset transistor resets the floating diffusion region 137 to a predetermined charge level before each charge transfer from the photodiode 131. Note that contacts 132 are formed in a not-shown insulating layer to connect to the respective gates and other connection lines in the CMOS sensor. Therefore, the contacts 132 implement electric connection to, for example, the source/drain region 133, the floating diffusion region 137, and other interconnects.
FIGS. 15A and 15B are schematic cross-sectional views showing a main part of the solid-state image sensor shown in FIG. 14. FIG. 15A shows a cross section corresponding to line XVa-XVa in FIG. 14, and FIG. 15B shows a cross section corresponding to line XVb-XVb in FIG. 14.
In the cross section of FIG. 15A, the photodiode 131 is formed in an element formation region in a p-type region 110 formed on the not-shown substrate. In other words, the photodiode 131 is formed in a region surrounded by a trench isolation region 119. The trench isolation region 119 is formed by filling a trench 119a with a dielectric material, and serves as an element isolation region. The photodiode 131 is formed by a photosensitive region, that is, a p-n-p junction region formed by a p-type region 127, an n-type region 121, and the p-type region 110. Since the photodiode 131 includes two p-type regions 127, 110, the n-type region 121 is completely depleted at a pinning voltage. The floating diffusion region 137 is formed in a surface region of the p-type region 110 so as to be adjacent to the n-type region 121. An n-type control implantation layer 123 adjacent to the n-type region 121 and the floating diffusion region 137 is also formed in the surface region of the p-type region 110. The transfer gate 125 is formed on the surface region of the p-type region 110 with a gate insulating film 124 interposed therebetween so as to extend over the photodiode region 131, the floating diffusion region 137, and the control implantation layer 123. Sidewalls 130 are formed on the sidewalls of the transfer gate 125.
In the cross section of FIG. 15B, on the other hand, the control implantation layer 123 is formed in the surface region of the p-type region 110 surrounded by the trench isolation region 119. The transfer gate 125 is formed on the surface region of the p-type region 110 with the gate insulating film 124 interposed therebetween so as to cover the control implantation layer 123. The transfer gate 125 is formed so that both ends of the transfer gate 125 are located on the trench isolation region 119.
In the conventional CMOS image sensor having the above structure, incident light causes electrons to gather in the n-type region 121. A maximum output signal, which is generated by the source follower transistor having the gate 135, is proportional to the number of electrons to be discharged from the n-type region 121. The maximum output signal increases with increase in electron capacitance or acceptability of the n-type region 121 for acquiring electrons. The electron capacitance of the photodiode 131 typically depends on the doping level of the image sensor and the impurities which are implanted into an active layer.
The trench isolation region 119, which is provided as a physical barrier for insulating adjacent pixel cells from each other, is formed by a typical STI (Shallow Trench Isolation) method by first forming a trench 119a in the substrate by etching, then filling the trench 119a with a dielectric material such as silicon dioxide (SiO2) by a CVD (Chemical Vapor Deposition) method, and planarizing the surface.
A problem in the formation of the trench isolation region 119 having the above structure is that, when ions are implanted into a region close to the ends or the sidewall portions of the trench 119a, a leakage current is generated in a junction region between the element formation region and the trench isolation region 119. Moreover, a dominant crystal face along the sidewalls of the trench isolation region 119 has a higher silicon density than that of the adjacent substrate. Therefore, a high density of trap sites is produced along the sidewalls of the trench isolation region 119. These trap sites are normally uncharged, but are charged when electrons and holes are trapped in the trap sites. These trapped carriers add charges to the device, and contribute to fixed charges of the device, whereby the threshold voltage of the device changes. When the trap sites are formed along the sidewalls of the trench isolation region 119, current generation along and near the trench sidewalls becomes very high. The current generated from the trap sites inside or near the photodiode deletion region causes a dark current.
In manufacturing of CMOS image sensors, it is important to implement a structure which minimizes a dark current in the photodiode. The dark current is generally caused by leakage in the charge accumulating region of the photodiode 131, which is strongly dependent on the impurity profile of the CMOS image sensor. Moreover, as described above, defects and trap sites inside or near the depletion region of the photodiode strongly affect the magnitude of the dark current generated. In other words, the dark current is generated by a current generated from the trap sites inside or near the depletion region of the photodiode, generation of band-to-band tunneling induced carriers due to high electric fields in the depletion region, junction leakage generated from the sidewalls of the photodiode, and leakage from a junction region of the trench isolation region 119, such as stress induced and trap assisted tunneling.
In the above conventional CMOS image sensor, an inactive layer 117 is formed to suppress generation of the dark current. As shown in FIGS. 15A and 15B, the inactive layer 117 is formed by implanting impurities into the bottom and sidewall portions of the trench 119a before the trench 119a is filled with the dielectric material. The impurities implanted in the bottom and sidewall portions of the trench 119a have an opposite conductivity type to that of impurities implanted in the charge accumulating region of the photodiode 131 (see, e.g., Published Japanese Translation of PCT International Application No. 2006-521697).